Comparative study of 16-bit adder using reversible logic gates
| dc.contributor.author | Shaikh, Afzal | |
| dc.contributor.author | Surve, Zaid (15DET113) | |
| dc.contributor.author | Khan, Faraz (15ET19) | |
| dc.contributor.author | Ansari, Saddam (16DET75) | |
| dc.contributor.author | Khan, Mohammad Ibrahim (16DET94) | |
| dc.date.accessioned | 2021-11-09T06:31:22Z | |
| dc.date.available | 2021-11-09T06:31:22Z | |
| dc.date.issued | 2020-05 | |
| dc.description.abstract | A reversible logic gate is a gate in which the output is guaranteed, but the input is not confirmed, in other words, reversible functions are those that perform permutations of the set of input vectors. Reversible Gates are circuits in which outputs are equal to the number of inputs, and there is one to one correspondence between the vectors of inputs and outputs. Reversible logic circuits have emerged as a promising technology has deficient power consumption with high speed and less delay, which is in demand with the increasing universal growth. Reversible logic Gates have its application in low power CMOS, Quantum Computing, Nanotechnology, and Optical Communication. As we know, the Reversible logic circuits deal with low power consumption with high speed and less delay we are going to design and analysis of 16-bit Full Adder using Reversible logic gates, and we need to observe the result and compare with conventional logic gates and observe the essential parameters between both designs. | en_US |
| dc.identifier.uri | http://localhost:8080/xmlui/handle/123456789/3622 | |
| dc.language.iso | en | en_US |
| dc.publisher | AIKTC | en_US |
| dc.subject | Project Report - EXTC | en_US |
| dc.title | Comparative study of 16-bit adder using reversible logic gates | en_US |
| dc.type | Other | en_US |