Design of ADC using CMOS for wireless communication
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Date
2017-05
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AIKTC
Abstract
In the current technical era, the technology advancement leads most of the
applications demanding for a reduction in the whole size of the system in terms
of its space occupied in any device. Mobile applications are one of the apt
scenarios for this category. Apart from the size reductions due to the technology
advancement, it also calls in for the reduction in the power consumption.
The Data Converters section, besides being very power hungry, it is also usually
extremely power hungry in comparison with the other blocks of any architecture
and that’s why low power has also become a tough requirement in most of the
systems. The total power consumption of the system being maintained in a low
figure has almost become a mandatory specification in many applications.
The SAR Analog to Digital Converter architecture is chosen in this master
thesis project, as it is one of the very successful moderate resolution achievable
converter system present among all the data converter architectures. The
schematic model of the entire system is implemented in Cadence system in
order to fulfil the technical requirements of the project.
The SAR architecture is implemented in Cadence 180 nm technology and the
power supply used is 2.5 volts. A differential configuration of the whole system
is thoroughly studied and an equivalent single ended system is also studied,
implemented and measured in this project. The differential architecture is
studied in this project to learn the merits behind the differential architecture,
which basically avoid the linearity and offset errors raised in the single ended
architecture. The resolution for which the system is designed is 10 bits.
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Project Report - EXTC